`timescale 1ns / 1ps

module decoder_3_seg(
	input [2:0] binary,
	input extrabit,
	output reg [7:0] seg_ctrl;
	);
	always @(*) begin
		if (extrabit) begin
			seg_ctrl <= 8'b0000_0010;
		end else begin
			case (display_num)
				3'b000: seg_ctrl <= 8'b1111_1100;
            	3'b001: seg_ctrl <= 8'b0110_0000;
				3'b010: seg_ctrl <= 8'b1101_1010;
            	3'b011: seg_ctrl <= 8'b1111_0010;
				3'b100: seg_ctrl <= 8'b0110_0110;
            	3'b101: seg_ctrl <= 8'b1011_0110;
				3'b110: seg_ctrl <= 8'b1011_1110;
            	3'b111: seg_ctrl <= 8'b1110_0000;
            	default: seg_ctrl <= 8'b0000_0000;
			endcase
		end
	end
endmodule

